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Integrated Circuit Systems, Inc.
ICS8545I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
FEATURES
* 4 LVDS outputs * 2 selectableLVCMOS/LVTTL clock inputs to support redundant or selectable frequency fanout applications * CLK1 and CLK2 can accept the following input levels: LVCMOS or LVTTL * Maximum output frequency: 650MHz * Translates LVCMOS/LVTTL input signals to LVDS levels * Output skew: 40ps (maximum) * Part-to-part skew: 500ps (maximum) * Propagation delay: 3.6ns (maximum) * 3.3V operating supply * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS8545I is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS clock fanout HiPerClockSTM buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8545I provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100. The ICS8545I accepts a LVCMOS input level and translates it to 3.3V LVDS output levels.
ICS
Guaranteed output and part-to-part skew characteristics make the ICS8545I ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN nD Q LE CLK1 CLK2 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
PIN ASSIGNMENT
GND CLK_EN CLK_SEL CLK1 nc CLK2 nc OE GND VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDD Q1 nQ1 Q2 nQ2 GND Q3 nQ3
CLK_SEL
ICS8545I
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm body package G Package Top View
OE
8545BGI
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1
REV. A DECEMBER 17, 2003
Integrated Circuit Systems, Inc.
ICS8545I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Type Power Input Input Input Unused Input Input Power Output Output Output Output Pulldown Pullup Pullup Pulldown Pulldown Description Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK2 input. When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels. LVCMOS / LVTTL clock input. Unused pins. LVCMOS / LVTTL clock input. Output enable. Controls enabling and disabling of outputs Q0, nQ0 thru Q3, nQ3. LVCMOS / LVTTL interface levels. Positive supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 9, 13 2 3 4 5, 7 6 8 10, 18 11, 12 14, 15 16, 17 19, 20 Name GND CLK_EN CLK_SEL CLK1 nc CLK2 OE VDD nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
8545BGI
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2
REV. A DECEMBER 17, 2003
Integrated Circuit Systems, Inc.
ICS8545I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Outputs Selected Source Q0:Q3 Hi Z CLK1 CLK2 CLK1 CLK2 Low Low ACTIVE ACTIVE nQ0:nQ3 Hi Z High High ACTIVE ACTIVE
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs OE 0 1 1 1 1 CLK_EN X 0 0 1 1 CLK_SEL X 0 1 0 1
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK1 and CLK2 inputs as described in Table 3B.
Disabled
Enabled
CLK1, CLK2
CLK_EN
nQ0:nQ3 Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK1 or CLK 2 0 1 Q0:Q3 LOW HIGH Outputs nQ0:nQ3 HIGH LOW
8545BGI
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3
REV. A DECEMBER 17, 2003
Integrated Circuit Systems, Inc.
ICS8545I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
4.6V -0.5V to VDD + 0.5V 10mA 15mA 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 52 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK1, CLK2 CLK_EN, CLK_SEL, OE CLK1, CLK2 CLK_EN, CLK_SEL, OE CLK1, CLK2, CLK_SEL CLK_EN, OE CLK1, CLK2, CLK_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -5 Test Conditions Minimum Typical 2 2 -0.3 -0.3 Maximum VDD + 0.3 VDD + 0.3 1.3 0.8 150 5 Units V V V V A A A A
-150 CLK_EN, OE VDD = 3.465V, VIN = 0V NOTE: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information, "Output Load Test Circuit".
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS IOZ IOFF IOSD IOS VOH VOL Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change High Impedance Leakage Current Power Off Leakage Differential Output Shor t Circuit Current Output Shor t Circuit Current Output Voltage High Output Voltage Low Test Conditions Minimum 200 1.125 -10 -20 Typical 280 1.25 5 1 1 -3.5 -3.5 1.34 1.06 Maximum 360 40 1.375 25 +10 +20 -5 -5 1.6 Units mV mV V mV A A mA mA V V
0.9
8545BGI
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4
REV. A DECEMBER 17, 2003
Integrated Circuit Systems, Inc.
ICS8545I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Test Conditions f 650MHz Minimum 1.4 Typical Maximum 650 3.6 40 20% to 80% @ f 266MHz f 266MHz 200 45 500 700 55 Units MHz ns ps ps ps % %
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle
tsk(o) tsk(pp) tR / tF
odc
f > 266MHz 40 60 All parameters measured at f 650MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2 of the input to the differential output crossing point. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8545BGI
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5
REV. A DECEMBER 17, 2003
Integrated Circuit Systems, Inc.
ICS8545I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VDD 3.3V
SCOPE
Qx
nQ0:nQ3
3.3V5% Power Supply Float GND + -
LVDS
nQx
V
Q0:nQ3
OD
Cross Points
V
GND
OS
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL OUTPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
nQx Qx nQy Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
CLK1, CLK2 nQ0:nQ3 Q0:Q3 tPD
80% Clock Outputs
80% VOD
20% tR tF
20%
PROPAGATION DELAY
8545BGI
OUTPUT RISE/FALL TIME
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6
REV. A DECEMBER 17, 2003
Integrated Circuit Systems, Inc.
ICS8545I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
VDD
nQ0:nQ4 Q0:Q4
out
DC Input
Pulse Width t
PERIOD
LVDS
out
VOS/ VOS
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH PERIOD
VDD
OFFSET VOLTAGE
VDD
out
out
DC Input
LVDS
DC Input
100
VOD/ VOD out
LVDS
out
IOSD
DIFFERENTIAL OUTPUT VOLTAGE
VDD out
DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT
IOS
DC Input
LVDS
IOSB out
LVDS
IOFF
VDD
OUTPUT SHORT CIRCUIT CURRENT
out
IOZ DC Input
POWER OFF LEAKAGE
3.3V5% POWER SUPPLY
+
Float GND
_
LVDS
IOZ
out
HIGH IMPEDANCE LEAKAGE CURRENT
8545BGI
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7
REV. A DECEMBER 17, 2003
Integrated Circuit Systems, Inc.
ICS8545I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
3.3V 3.3V LVDS_Driver + R1 100
-
100 Ohm Differential
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS8545I. In this example, the CLKx input is selected. The decoupling capacitors
should be physically located near the power pin. For ICS8545I, the unused clock outputs can be left floating.
Zo = 50 + 3.3V R12 1K 3.3V U1 1 2 3 4 5 6 7 8 9 10 GND CLK_EN CLK_SEL CLK1 NC CLK2 NC OE GND VDD Q0 nQ0 VDD Q1 nQ1 Q2 nQ2 GND Q3 nQ3 20 19 18 17 16 15 14 13 12 11 Zo = 50 R1 50 -
Ro ~ 7 Ohm
Zo = 50 Ohm 43
3.3V
R13 LVCMOS
3.3V R11 1K C1 0.1u
ICS8545I Zo = 50 3.3V R2 50 C2 0.1u C3 0.1u Zo = 50 +
FIGURE 3. ICS8545I LVDS BUFFER SCHEMATIC EXAMPLE
8545BGI
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8
REV. A DECEMBER 17, 2003
Integrated Circuit Systems, Inc.
ICS8545I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
114.5C/W 73.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8545I is: 644
8545BGI
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9
REV. A DECEMBER 17, 2003
Integrated Circuit Systems, Inc.
ICS8545I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX
Reference Document: JEDEC Publication 95, MO-153
8545BGI
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10
REV. A DECEMBER 17, 2003
Integrated Circuit Systems, Inc.
ICS8545I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Marking Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel Count 72 per tube 2500 Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS8545BGI ICS8545BGIT ICS8545BGI ICS8545BGI
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8545BGI
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11
REV. A DECEMBER 17, 2003

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